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All Rights Reserved Lab Overview • • • Generate a dual-port block RAM core Replace an instantiated library primitive with the core Perform behavioral simulation on the design – Testbench file provided CORE Generator System - 9 - 35 © 2003 Xilinx, Inc. All Rights Reserved General Flow Step 1: Review the design Step 2: Generate the core Step 3: Instantiate block RAM core into Verilog or VHDL source Step 4: Perform behavioral simulation CORE Generator System - 9 - 36 © 2003 Xilinx, Inc. All Rights Reserved Agenda Section 1 : Optimize Your Design for Xilinx Architecture – Core Generator System • Lab : Core Generator System Flow Section 2 : Achieving Timing Closure – – – Timing Closure with Timing Analyzer Global Timing Constraints • Lab : Global Timing Constraints Advance Timing Constraints • Lab : Achieving Timing Closure with Advance Constraints Section 3 : Improve Your Timing – Floorplanner • Lab: Floorplanner Section 4 : Reduce Implementaion Time – Incremental Design Techniques • – Lab : IDT Flow Modular Design Techniques • Lab : MDT Flow Timing Closure with Timing Analyzer - 2 © 2003 Xilinx, Inc.

All Rights Reserved Cross Probing • • • Shows the placement of logic in a delay path To enable cross probing, use the command: View → Floorplanner for Cross probing Click highlighted text – The corresponding logic is selected in the Floorplanner Timing Closure with Timing Analyzer - 9 © 2003 Xilinx, Inc. All Rights Reserved Timing Report Structure • Timing Constraints – – • Data Sheet Report – • Setup, hold, and clock-to-out times for each I/O pin Timing Summary – • Number of paths covered and number of paths that failed for each constraint Detailed descriptions of the longest paths Number of errors, Timing Score Timing Analyzer Settings – Allows you to easily duplicate the report Timing Closure with Timing Analyzer - 10 © 2003 Xilinx, Inc.

Com Software manuals: CORE Generator Guide CORE Generator System - 9 - 29 © 2003 Xilinx, Inc. All Rights Reserved Agenda Section 1 : Optimize Your Design for Xilinx Architecture – Core Generator System • Lab : Core Generator System Flow Section 2 : Achieving Timing Closure – – – Timing Closure with Timing Analyzer Global Timing Constraints • Lab : Global Timing Constraints Advance Timing Constraints • Lab : Achieving Timing Closure with Advance Constraints Section 3 : Improve Your Timing – Floorplanner • Lab: Floorplanner Section 4 : Reduce Implementaion Time – Incremental Design Techniques • – Lab : IDT Flow Modular Design Techniques • Lab : MDT Flow CORE Generator System - 9 - 30 © 2003 Xilinx, Inc.

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